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In page Hitachi 6309:
"Although it is a dynamic design (the datasheet[1] specifies a 500 kHz minimum clocking frequency and it will lose its state when the clock speed is too low), it can be paused for up to 15 cycles.[citation needed] This is useful for direct memory access as it allows external devices to pause the CPU to release the memory bus, read or write small amounts of memory, and then unpause the CPU again. No other logic is required.
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